This invention relates to an interface circuit for an integrated injection logic circuit as used in an interface between the integrated injection logic circuit and the other circuit.
A fundamental circuit of the integrated injection logic circuit (I.sup.2 L circuit) comprises, as shown in FIG. 1, a PNP transistor Q.sub.I as an injector and an output NPN transistor Q.sub.0 having at least one open collector. Since a greater load cannot be driven with one transistor Q.sub.0, an interface circuit is required for the I.sup.2 L circuit to drive the other circuit, for example, a TTL circuit.
FIGS. 2 and 3 each show a conventional interface circuit as used in an interface circuit between an I.sup.2 L circuit and a TTL circuit. The interface circuit as shown in FIG. 2 comprises three NPN transistors Q.sub.1 to Q.sub.3, three resistors R.sub.1 to R.sub.3 and one diode D.sub.1. An output of an I.sup.2 L inverting gate G as configured in FIG. 1 is applied to the base of the NPN transistor Q.sub.1. The interface circuit as shown in FIG. 3 comprises two PNP transistors Q.sub.4, Q.sub.5, two NPN transistors Q.sub.6, Q.sub.7 and seven resistors R.sub.4 to R.sub.10. An output of an I.sup.2 L inverting gate G as configured in FIG. 1 is applied through the resistor R.sub.5 to the base of the PNP transistor Q.sub.4. In the conventional interface circuit it is not possible to obtain an arbitrary output voltage and there is a disadvantage that high and low level output voltages are fixed to certain levels. In the interface circuit of FIG. 2, for example, a high level output voltage is V.sub.CC -2V.sub.F and a low level output voltage is V.sub.CE (sat) (Q.sub.3). In the interface circuit as shown in FIG. 3 the high level output voltage is V.sub.CC -V.sub.CE (sat)(Q.sub.5)-V.sub.BE (Q.sub.7) and the low level output voltage is zero (ground potential).